The present invention relates to charge pumps for outputting boosted voltages and, more particularly, to a charge pump operable at even low power supply voltages.
Charge pumps for boosting a power supply voltage to output a high voltage are used in, for example, nonvolatile semiconductor storage devices such as flash memories. First, the structure of a flash memory will be described.
The structure of a memory cell of the flash memory is schematically shown in FIG. 2. This memory cell 1 has a control gate 2, a floating gate 3, a source 4, and a drain 5. The memory cell 1 stores data of "1" or "0" by electrons injected into the floating gate 3. In the flash memory, there are provided a plurality of memory cell blocks each having such flash memory cells arrayed into an m.times.n matrix. In each memory cell block, n control gates 2 are connected to each of m word lines, m drains 5 are connected to each of n bit lines, and the sources 4 are connected all in common. Because the sources 4 are connected in common in each block, memory cells are erased collectively block by block and cannot be erased bit by bit, as explained later.
Next, read, write, and erase operations of the flash memory will be briefly described.
Referring to the read operation, when a read signal comprising a control signal, an address signal and the like is fed from outside, a high voltage (e.g., 5 V) is applied to the control gate 2, a low voltage (e.g., 1 V) to the drain 5, and a low voltage (e.g., 0 V) to the source 4. Then, by comparing a current flowing between the source 4 and the drain 5 of a memory cell to be read with a current flowing through a reference memory cell by a sense amplifier, data discrimination between a "1" and a "0" is performed. After that, read data from the memory cell is output to the outside, where the read operation is completed.
The write operation is carried out as follows.
A control signal, data and an address signal are fed from outside of the flash memory, and a high voltage (e.g., 12 V) is applied to the control gate 2, a high voltage (e.g., 7 V) to the drain 5, and a low voltage (e.g., 0 V) to the source 4. When this occurs, hot electrons generated in proximity to a drain junction are injected to the floating gate 3 due to the high voltage applied to the control gate 2. After this, with the write state turned off, a verify operation is performed. If the written cells are successful in verification, the write operation is completed. If a cell fails in verification, the write operation is performed again and then a verify operation is performed. This process is repeated a prescribed number of times. Then, if the verification has resulted in a failure, "Write Error Status" is output back to outside.
Lastly, the erase operation will be described.
The erase operation is carried out block by block. A control signal, an address signal, and erase data are fed from outside. Also, a low voltage (e.g., -10 V) is applied to the control gate 2, the drain 5 is put into a floating state, and a high voltage (e.g., 6 V) is applied to the source 4. When such voltages are applied, a high electric field is generated between the floating gate 3 and the source 4, making it possible to pull out the electrons from the floating gate 3 to the source 4 by a tunneling phenomenon. After this, with the erase state turned off, a verify operation is performed as in the write operation. If all the memory cells in an erase block are successful in verification, the erase operation is completed. If the erase block fails in verification, the erase operation is done again and then a verify operation is performed. This process is repeated a prescribed number of times. Then, if the verification has resulted in a failure, "Erase Error Status" is output back to outside.
In this connection, the high positive voltages (12 V, 7 V, etc.) and the negative voltages (-10 V, etc.) fed to the control gate 2, the drain 5 and the source 4 of the memory cell 1 in the read, write and erase operations and the like as described above are, generally, generated and applied by a charge pump.
An example of prior art high voltage charge pumps is shown in FIG. 3.
In the charge pump, a plurality of boosting stages stg1, . . . , stg8 (only 8 stages are shown in the figure) are connected in series, each stage comprising N-channel MOS transistors N1 and N2, and capacitors C1 and C2. To the capacitors C1 and C2 of the individual stages, clock signals CLK1 and CLK2, or CLK3 and CLK4, which are shown in FIGS. 4A, 4B, 4C and 4D, are applied, respectively.
Operation of this high voltage charge pump is briefly explained.
The clock signals CLK1, CLK2, CLK3 and CLK4 to be input to the boosting stages are square waves each having appropriate periods and cycles of "H" and "L", as depicted in FIGS. 4A-4D. This charge pump accumulates electric charges in the capacitor C2 of, firstly stg1, and then stg2, stg3, . . . , successively, to finally obtain a desired high voltage. In the charge pump, in receiving a boosted voltage in the capacitor C2 of one stage from the preceding-stage capacitor C2, any voltage drop of the boosted voltage delivered from the preceding stage is suppressed by timely changing the clock signal CLK1 or CLK3 input to the capacitor C1 from a ground level to a power supply voltage level. After that, the boosted voltage delivered to the capacitor C2 is further boosted by changing the input clock signal CLK2 or CLK4 from the ground level to the power supply voltage level. As a result, the potential boosted at the preceding stage is boosted further by a voltage approximately equal to the magnitude of the power supply voltage. As this sequence of operations is repeated, the output voltage of each pump stage increases with increasing number of stages of the pump.
However, as the voltage generated by the high voltage charge pump increases, threshold voltages of the transistors N1, N2 increase due to the backgating effect. That is, the higher the voltage generated by each stage of the high voltage charge pump becomes, the higher the threshold voltages of the transistors N1, N2 of the stage become. Accordingly, in the pump final stage where the highest voltage is generated, the threshold voltages of the transistors become the largest by the backgating effect. When the threshold voltages of the transistors become equal to the voltages of the clock signals input to the pump, the high voltage charge pump cannot boost the voltage any more.
As an example, if a power supply voltage is about 5 V, the voltages of the clock signals are enough large relative to the threshold voltages of the transistors. Thus, there occurs no voltage drop of a boosted voltage at the time of charge delivery. In contrast to this, if a power supply voltage is as low as about 3 V, a voltage drop will occur in the final stage at the delivery of boosted charge from the preceding stage, resulting in a low boosting efficiency of the pump. Further, with an even lower power supply voltage of about 2 V, the threshold voltages of the transistors in the final stage become approximately equal to the voltages of the clock signals input to the pump, making it impossible to achieve a voltage higher than the voltage delivered from the preceding stage. This means that even if further pump stages are added, the voltage cannot be boosted any more. That is, the boosted voltage that could be generated with the charge pump at a power supply voltage of 5 V can no longer be generated with a low voltage power supply of about 2 V because of a great effect of an increase in threshold voltage of the transistors. Therefore, in order to design a low-power-supply-voltage and low-power-consumption device, there is a need of decreasing the threshold voltages of the transistors.
As an example of high voltage charge pumps operable with a low-voltage power supply that can cope with the increase in the threshold voltage of transistors due to the backgating effect, a circuit disclosed in Japanese Patent Laid-Open Publication HEI 6-261538 is known.
The high voltage charge pump disclosed in Japanese Patent Laid-Open Publication HEI 6-261538 is additionally equipped with a circuit for boosting the clock signal voltage. With this arrangement, any drop of a boosted potential at the time of the delivery from one stage to another is suppressed even with a low voltage power supply, so that the boosting efficiency is increased.
In the above prior art high voltage charge pump, however, a clock signal boosting circuit can generate no more than a single boosted voltage. That is, the prior art charge pump is only capable of generating a boosted voltage which is the power supply voltage multiplied by a constant. In such a high voltage charge pump, boosting of the clock signal voltage is effective as far as a particular low-voltage power supply voltage is concerned. When a wider range of power supply voltages is involved, however, boosted clock signal voltages may become too high with higher power supply voltages. In such a case, high voltages would be applied to elements such as transistors, capacitors and the like constituting the circuit, and in worst cases, the elements would be broken down, adversely affecting the device reliability. Besides, normally, as the amount of current necessary for the boosted voltage increases, the capacity of the boosting capacitors increases. Whereas the boosting capacitors need to be charged by the circuit that boosts the clock signal voltage, the capacity for boosting the clock signal voltage needs to be larger than the capacity of the boosting capacitor of the pump, which leads to an increase in layout area.
Furthermore, Japanese Patent Laid-Open Publication HEI 9-7384 discloses a phase signal generating circuit for use in a charge-pump type negative voltage supply circuit, in which clock signals (phase signals) corresponding to low power supply voltages and high power supply voltages, respectively, are generated. This circuit, unfortunately, has a problem in that the circuit scale is large, which leads to an increase in layout area. Also, because of the arrangement that all pump stages of the negative voltage charge pump are individually connected to the phase signal generating circuit, the layout area is further increased. Moreover, because a boost phase signal varies from a negative potential to power supply potential (Vcc), a back flow of a current tends to occur in the phase signal generating circuit, causing circuit troubles.